As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option is an Information Handling System (IHS). An IHS generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes. Because technology and information handling needs and requirements may vary between different applications, IHSs may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in IHSs allow for IHSs to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, global communications, etc. In addition, IHSs may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
An IHS may be designed with a multi-core processor. A multi-core processor is a single computing component with two or more independent processing cores that are able to read and execute program instructions or software code. These multiple cores can run multiple instructions concurrently, thus increasing the overall processing speed for programs. Multiple cores typically are integrated onto a single integrated circuit die or integrated circuit or onto multiple dies in a single chip package, generally referred to as the IHS's Central Processing Unit (CPU). In some cases, a single IHS may include two or more multi-core CPUs.
Each multi-core processor may include one or more “CPU sockets.” Each CPU socket may in turn have, for example, one or more processor cores, one or more memory controllers (which allow for dual in-line memory module(s) external to CPU socket), and one or more Peripheral Component Interconnect Express (PCIe) Input/Output (I/O) lanes.
The inventors hereof have recognized that certain software products (e.g., virtualization and virtual machine software) is licensed based upon a number of CPU sockets present in a given IHS, while certain other software products (certain database, Computer-aided design (CAD), Electronic design automation (EDA), etc.) are licensed based on number of CPU cores present in the given IHS. A good portion of these licensed software benefits from larger amounts of system memory. As a result, majority of customers end up purchasing servers with more CPU sockets just to get adequate amount of system memory. Lately, the number of cores in CPU sockets has been doubling every 2-3 years. However, the available memory and I/O circuitry has not historically increased at the same rate as the number of cores. In fact, in most virtualized applications, often the most significant performance limiting factor is insufficient memory; not the available number of cores.
Accordingly, the inventors hereof have identified a demand for larger memories (e.g., 24 DIMMs per socket instead of across two sockets) and/or I/O ports to be used with a smaller number of CPU sockets (e.g., one or two) within a multi-core processor, in order to reduce software licensing costs in certain applications.